Semiconductor memory device and method of manufacturing the same

ABSTRACT

A semiconductor memory device includes first and second element isolation insulating films, first and second gate insulating films, first and second gate wiring and first and second mask layer. First and second upper surfaces of the first and second element isolation insulating films are higher than an upper surface of the substrate, first and second bottom surfaces of the first and second element isolation insulating films are lower than the upper surface of the substrate, a second height from the upper surface of the substrate to the second upper surface is larger than a first height from the upper surface of the substrate to the first upper surface. A height from the upper surface of the substrate to an upper surface of the first mask layer equals a height from the upper surface of the substrate to an upper surface of the second mask layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromprior Japanese Patent Application No. 2005-322100, filed Nov. 7, 2005,the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a nonvolatile semiconductor memorydevice having a layered gate structure with a shallow trench isolation(STI) element isolation insulating film and a method of manufacturingthe same.

2. Description of the Related Art

Along with the recent size reduction of semiconductor memory devices,element isolation by self-aligned shallow trench isolation (STI) isbecoming popular. In element isolation using STI, the width of STI inthe memory cell region is minimized, and the STI is made shallow tominimize the aspect ratio in gap filling so as to ensure the STI gapfilling capability. In the peripheral circuit portion to control thememory cell, however, the dielectric isolation between elements is morenecessary than memory cells. To ensure the dielectric isolation, the STIin the peripheral circuit region is deeper than the STI in the memorycell region (see e.g., Jpn. Pat. Appln. KOKAI Publication No.2002-368077).

However, if the dielectric isolation in the peripheral circuit region isto be further improved, the STI cannot be deepened because of therestrictions on the STI gap filling capability. Instead, in theperipheral circuit region, the STI is made higher than in the memorycell region. In this case, however, the following problems are posed.

The STI is high in the peripheral circuit region and low in the memorycell region. For this reason, the height from the surface of the siliconsubstrate to the mask material of the gate wiring is large in theperipheral circuit region and small in the memory cell region. If thegate wiring is to be buried by an insulating film, and planarization bychemical mechanical polishing (CMP) is to be executed, a barrier layerdeposited on the mask material of the gate wiring is used as the stopperof CMP. However, since the height to the mask material changes betweenthe memory cell region and the peripheral circuit region, the barrierlayer in the peripheral circuit region where the mask material is highis excessively polished by CMP. For this reason, the barrier layer onthe peripheral circuit region side becomes thin at the boundary betweenthe memory cell region and the peripheral circuit region, or the barrierlayer is completely lost. In addition, the difference in height to thebarrier layer between the peripheral circuit region and the memory cellregion (the step difference between the memory cell region and theperipheral circuit region) influences metal interconnection formation tobe performed later. Hence, a resolution failure occurs in lithography atthe step portion of the boundary region.

BRIEF SUMMARY OF THE INVENTION

According to a first aspect of the present invention, there is provideda semiconductor memory device comprising a semiconductor substrate whichhas a first region and a second region, a first element isolationinsulating film which is formed in the semiconductor substrate in thefirst region, includes a first upper surface higher than an uppersurface of the semiconductor substrate and a first bottom surface lowerthan the upper surface of the semiconductor substrate, and has a firstheight from the upper surface of the semiconductor substrate to thefirst upper surface, a second element isolation insulating film which isformed in the semiconductor substrate in the second region, includes asecond upper surface higher than the upper surface of the semiconductorsubstrate and a second bottom surface lower than the upper surface ofthe semiconductor substrate, and has a second height from the uppersurface of the semiconductor substrate to the second upper surface, thesecond height being larger than the first height, a first gateinsulating film which is formed on the semiconductor substrate in thefirst region, a first gate wiring which is formed on the first gateinsulating film, a first mask layer which is formed on the first gatewiring, a second gate insulating film which is formed on thesemiconductor substrate in the second region, a second gate wiring whichis formed on the second gate insulating film, and a second mask layerwhich is formed on the second gate wiring, wherein a height from theupper surface of the semiconductor substrate to an upper surface of thefirst mask layer equals a height from the upper surface of thesemiconductor substrate to an upper surface of the second mask layer.

According to a second aspect of the present invention, there is provideda semiconductor memory device manufacturing method comprising, in asemiconductor substrate having a first region and a second region,forming a first gate insulating film on the semiconductor substrate inthe first region and forming a second gate insulating film on thesemiconductor substrate in the second region, forming a first gatewiring material on the first gate insulating film and the second gateinsulating film, forming a first element isolation insulating film bypartially removing the first gate wiring material, the first gateinsulating film, and the semiconductor substrate and forming a secondelement isolation insulating film by partially removing the first gatewiring material, the second gate insulating film, and the semiconductorsubstrate, making a first height from an upper surface of thesemiconductor substrate to an upper surface of the first elementisolation insulating film smaller than a second height from the uppersurface of the semiconductor substrate to an upper surface of the secondelement isolation insulating film by removing an upper portion of thefirst element isolation insulating film, forming a second gate wiringmaterial, third gate wiring material, and first mask layer sequentiallyin the first region and forming a fourth gate wiring material and asecond mask layer sequentially in the second region, and removing anupper portion of the first mask layer to make a height from the uppersurface of the semiconductor substrate to an upper surface of the firstmask layer equal to a height from the upper surface of the semiconductorsubstrate to an upper surface of the second mask layer.

According to a third aspect of the present invention, there is provideda semiconductor memory device manufacturing method comprising, in asemiconductor substrate having a first region and a second region,forming a first gate insulating film on the semiconductor substrate inthe first region and forming a second gate insulating film on thesemiconductor substrate in the second region, forming a first gatewiring material on the first gate insulating film and the second gateinsulating film, forming a first element isolation insulating film bypartially removing the first gate wiring material, the first gateinsulating film, and the semiconductor substrate and forming a secondelement isolation insulating film by partially removing the first gatewiring material, the second gate insulating film, and the semiconductorsubstrate, making a first height from an upper surface of thesemiconductor substrate to an upper surface of the first elementisolation insulating film smaller than a second height from the uppersurface of the semiconductor substrate to an upper surface of the secondelement isolation insulating film by removing an upper portion of thefirst element isolation insulating film, forming a second gate wiringmaterial in the first region, forming a third gate wiring material inthe second region, and making upper surfaces of the second gate wiringmaterial and the third gate wiring material flush with each other, andforming a first mask layer on the second gate wiring material andforming a second mask layer on the third gate wiring material.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1 is a sectional view showing a semiconductor memory device havinga memory cell region and peripheral circuit region according to thefirst embodiment of the present invention;

FIG. 2A is a sectional view showing the semiconductor memory device inthe peripheral circuit region taken along a line IIA-IIA in FIG. 1;

FIG. 2B is a sectional view showing the semiconductor memory device inthe peripheral circuit region taken along a line IIB-IIB in FIG. 1;

FIG. 2C is a sectional view showing the semiconductor memory device inthe memory cell region taken along a line IIC-IIC in FIG. 1;

FIG. 2D is a sectional view showing the semiconductor memory device inthe memory cell region taken along a line IID-IID in FIG. 1;

FIGS. 3, 4, 5, 6, 7, and 8 are sectional views showing steps inmanufacturing the semiconductor memory device having the memory cellregion and peripheral circuit region according to the first embodimentof the present invention;

FIG. 9A is a sectional view showing steps in manufacturing thesemiconductor memory device having the memory cell region and peripheralcircuit region according to the first embodiment of the presentinvention following FIG. 8;

FIG. 9B is a sectional view showing the semiconductor memory device inthe peripheral circuit region taken along a line IXB-IXB in FIG. 9A;

FIG. 9C is a sectional view showing the semiconductor memory device inthe memory cell region taken along a line IXC-IXC in FIG. 9A;

FIG. 10A is a sectional view showing steps in manufacturing thesemiconductor memory device having the memory cell region and peripheralcircuit region according to the first embodiment of the presentinvention following FIG. 9A;

FIG. 10B is a sectional view showing the semiconductor memory device inthe peripheral circuit region taken along a line XB-XB in FIG. 10A;

FIG. 10C is a sectional view showing the semiconductor memory device inthe memory cell region taken along a line XC-XC in FIG. 10A;

FIG. 11A is a sectional view showing steps in manufacturing thesemiconductor memory device having the memory cell region and peripheralcircuit region according to the first embodiment of the presentinvention following FIG. 10A;

FIG. 11B is a sectional view showing the semiconductor memory device inthe peripheral circuit region taken along a line XIB-XIB in FIG. 11A;

FIG. 11C is a sectional view showing the semiconductor memory device inthe memory cell region taken along a line XIC-XIC in FIG. 11A;

FIG. 12 is a sectional view showing a semiconductor memory device havinga memory cell region and peripheral circuit region according to thesecond embodiment of the present invention;

FIGS. 13 and 14 are sectional views showing steps in manufacturing thesemiconductor memory device having the memory cell region and peripheralcircuit region according to the second embodiment of the presentinvention;

FIG. 15A is a sectional view showing steps in manufacturing thesemiconductor memory device having the memory cell region and peripheralcircuit region according to the second embodiment of the presentinvention following FIG. 14;

FIG. 15B is a sectional view showing the semiconductor memory device inthe peripheral circuit region taken along a line XVB-XVB in FIG. 15A;

FIG. 15C is a sectional view showing the semiconductor memory device inthe memory cell region taken along a line XVC-XVC in FIG. 15A;

FIG. 16A is a sectional view showing steps in manufacturing thesemiconductor memory device having the memory cell region and peripheralcircuit region according to the second embodiment of the presentinvention following FIG. 15A;

FIG. 16B is a sectional view showing the semiconductor memory device inthe peripheral circuit region taken along a line XVIB-XVIB in FIG. 16A;

FIG. 16C is a sectional view showing the semiconductor memory device inthe memory cell region taken along a line XVIC-XVIC in FIG. 16A; and

FIG. 17 is a sectional view showing steps in manufacturing thesemiconductor memory device having the memory cell region and peripheralcircuit region according to the second embodiment of the presentinvention following FIG. 16A.

DETAILED DESCRIPTION OF THE INVENTION

The embodiments of the present invention will be described below withreference to the accompanying drawing. The same reference numeralsdenote the same parts throughout the drawing.

First Embodiment

A nonvolatile semiconductor memory according to the first embodiment hastwo kinds of self-aligned shallow trench isolation (STI) elementisolation insulating films (element isolation regions) which are shallowin a memory cell region and deep in a peripheral circuit region. Theheight of STI under the gate wiring in the peripheral circuit region islarger than that of STI under the gate wiring in the memory cell region.The height from the upper surface of a semiconductor substrate to themask layer of the gate wiring is equal in the memory cell region andperipheral circuit region.

FIG. 1 is a sectional view showing a semiconductor memory device havinga memory cell region and peripheral circuit region according to thefirst embodiment of the present invention. FIG. 2A is a sectional viewshowing the semiconductor memory device in the peripheral circuit regiontaken along a line IIA-IIA in FIG. 1. FIG. 2B is a sectional viewshowing the semiconductor memory device in the peripheral circuit regiontaken along a line IIB-IIB in FIG. 1. FIG. 2C is a sectional viewshowing the semiconductor memory device in the memory cell region takenalong a line IIC-IIC in FIG. 1. FIG. 2D is a sectional view showing thesemiconductor memory device in the memory cell region taken along a lineIID-IID in FIG. 1. The semiconductor memory device according to thefirst embodiment will be described below.

As shown in FIGS. 1 and 2A to 2D, the first embodiment is directed to anonvolatile semiconductor memory having a memory cell region andperipheral circuit region. Examples of the nonvolatile semiconductormemory are a NAND flash memory and NOR flash memory.

In the memory cell region, a tunnel insulating film 12 is formed on asemiconductor substrate (silicon substrate) 11. A floating gateelectrode FG is formed on the tunnel insulating film 12. An oxidenitride oxide (ONO) insulating film 21 is formed on the floating gateelectrode FG. A control gate electrode CG is formed on the ONOinsulating film 21. With this structure, a plurality of cell transistorsTr1 with a double gate structure are formed. The floating gate electrodeFG includes a polysilicon layer 14. The control gate electrode CGincludes two polysilicon layers 22 and 24. A WSi (tungsten silicide)film 25 is formed on the control gate electrode CG. A mask layer 26 isformed on the WSi film 25.

A plurality of element isolation insulating films STI1 with an STIstructure are formed in the semiconductor substrate 11 in the memorycell region. The element isolation insulating film STI1 has a firstportion STI1-A located under the control gate electrode CG and a secondportion STI1-B located under a spacer 29. The element isolationinsulating film STI1 at an end of each of the plurality of celltransistors Tr1 includes the first portion STI1-A and second portionSTI1-B. The upper surface of the first portion STI1-A of the elementisolation insulating film STI1 is higher than the upper surface of thesemiconductor substrate 11 and is flush with, e.g., the upper surface ofthe tunnel insulating film 12. The upper surface of the second portionSTI1-B of the element isolation insulating film STI1 is almost flushwith the upper surface of the semiconductor substrate 11. The bottomsurfaces of the first and second portions STI1-A and STI1-B of theelement isolation insulating film STI1 have the same depth. The bottomsurfaces are deeper than the upper surface of the semiconductorsubstrate 11 and also deeper than the bottom surface of the diffusionlayer (not shown) of the cell transistor Tr1.

In the memory cell region, the floating gate electrode FG and tunnelinsulating film 12 are self-aligned to the element isolation insulatingfilm STI1. For this reason, the width of the floating gate electrode FGand tunnel insulating film 12 in the gate width direction equals thedistance between the element isolation insulating films STI1.

In the peripheral circuit region, a gate insulating film 13 is formed onthe semiconductor substrate 11. A gate wiring G is formed on the gateinsulating film 13. Hence, a plurality of peripheral transistors Tr2 areformed. The gate wiring G includes the two polysilicon layers 14 and 24.The WSi film 25 is formed on the gate wiring G. The mask layer 26 isformed on the WSi film 25.

A plurality of element isolation insulating films STI2 with an STIstructure are formed in the semiconductor substrate 11 in the peripheralcircuit region. The element isolation insulating film STI2 has a firstportion STI2-A located under part of the gate wiring G (polysiliconlayer 24) and a second portion STI2-B located under the spacer 29. Theupper surface of the first portion STI2-A of the element isolationinsulating film STI2 is higher than the upper surface of thesemiconductor substrate 11 and is flush with, e.g., the upper surface ofthe polysilicon layer 14. The upper surface of the second portion STI2-Bof the element isolation insulating film STI2 is almost flush with theupper surface of the semiconductor substrate 11. The bottom surfaces ofthe first and second portions STI2-A and STI2-B of the element isolationinsulating film STI2 have the same depth. The bottom surfaces are deeperthan the upper surface of the semiconductor substrate 11 and also deeperthan the bottom surface of the diffusion layer (not shown) of theperipheral transistor Tr2.

In the peripheral circuit region, the polysilicon layer 14 of the gatewiring G and the gate insulating film 13 are self-aligned to the elementisolation insulating film STI2. For this reason, the width of thepolysilicon layer 14 of the gate wiring G and the gate insulating film13 in the gate width direction equals the distance between the elementisolation insulating films STI2.

A barrier layer 30 is formed on the mask layer 26 in the memory cellregion and peripheral circuit region. Insulating films 31 and 32 areformed on the barrier layer 30. Contacts C1 and C2 connected to the WSifilm 25 through the insulating film 32, barrier layer 30, and mask layer26 are formed. The contact C1 is located above the element isolationinsulating film STI1. The contact C2 is located above the elementisolation insulating film STI2.

In the above-described semiconductor memory device, a height h2 from theupper surface of the semiconductor substrate 11 to the upper surface ofthe mask layer 26 in the peripheral circuit region equals a height h1from the upper surface of the semiconductor substrate 11 to the uppersurface of the mask layer 26 in the memory cell region.

A height X2 (to be referred to as a height X2 of the element isolationinsulating film STI2 hereinafter) from the upper surface of thesemiconductor substrate 11 to the upper surface of the first portionSTI2-A of the element isolation insulating film STI2 in the peripheralcircuit region is larger than a height X1 (to be referred to as a heightX1 of the element isolation insulating film STI1 hereinafter) from theupper surface of the semiconductor substrate 11 to the upper surface ofthe first portion STI1-A of the element isolation insulating film STI1in the memory cell region.

The height X2 of the element isolation insulating film STI2 ispreferably twice or more the height X1 of the element isolationinsulating film STI1. The reason for this is as follows. The controlgate electrode CG and semiconductor substrate 11 in the memory cellregion are insulated by at least the tunnel insulating film 12 and ONOinsulating film 21. To obtain a corresponding breakdown voltage by thehigh-breakdown voltage peripheral transistor Tr2, the height X2 of theelement isolation insulating film STI2 must be equal to or more than(thickness of tunnel insulating film 12+thickness of ONO insulating film21).

The upper limit value of the height X2 of the element isolationinsulating film STI2 is preferably equal to or smaller than the heightof the polysilicon layer 14 of the gate wiring G. The reason for this isas follows. If the height X2 of the element isolation insulating filmSTI2 is larger than the height of the polysilicon layer 14, the heightof the gate wiring G becomes larger on the element isolation insulatingfilm STI2 than on the active region to generate a step difference.Hence, in CMP planarization of the buried insulating film 31, erosion(dishing) for the barrier layer 30 in the peripheral circuit regionoccurs.

The upper surface of the first portion STI1-A of the element isolationinsulating film STI1 is preferably, e.g., lower than a levelcorresponding to the thickness of the floating gate electrode FG(polysilicon layer 14) and equal to or higher than the upper surface ofthe tunnel insulating film 12. The upper surface of the first portionSTI2-A of the element isolation insulating film STI2 is preferably,e.g., higher than a level corresponding to about ½ the thickness of thepolysilicon layer 14 and equal to or lower than the upper surface of thepolysilicon layer 14.

A depth Y2 (to be referred to as a depth Y2 of the element isolationinsulating film STI2 hereinafter) from the upper surface of thesemiconductor substrate 11 to the bottom surface of the elementisolation insulating film STI2 in the peripheral circuit region islarger than a depth Y1 (to be referred to as a depth Y1 of the elementisolation insulating film STI1 hereinafter) from the upper surface ofthe semiconductor substrate 11 to the bottom surface of the elementisolation insulating film STI1 in memory cell region.

The depth Y2 of the element isolation insulating film STI2 is preferablyformed larger than the depth of a source/drain diffusion layer S/D ofthe high-breakdown-voltage peripheral transistor Tr2. The depth Y1 ofthe element isolation insulating film STI1 is preferably formed largerthan the depth of the source/drain diffusion layer S/D of the celltransistor Tr1.

The depth of the source/drain diffusion layer S/D of the peripheraltransistor Tr2 is preferably formed larger than the depth Y1 of theelement isolation insulating film STI1 and smaller than the depth Y2 ofthe element isolation insulating film STI2.

The depth of the source/drain diffusion layer S/D of the cell transistorTr1 is preferably formed smaller than the depth Y1 of the elementisolation insulating film STI1. For example, the depth of thesource/drain diffusion layer S/D of the cell transistor Tr1 ispreferably formed to be about ⅔ the depth Y1 of the element isolationinsulating film STI1.

In the memory cell region and peripheral circuit region, the aspectratio of the minimum space portion in the peripheral circuit region mustbe larger than the aspect ratio of the minimum space portion in thememory cell. For this reason, the ratio of the depth Y1 of the elementisolation insulating film STI1 to the depth Y2 of the element isolationinsulating film STI2 is preferably given by

(depth Y1+height of polysilicon layer 22 of control gate electrodeCG)/(minimum width of element isolation insulating film STI1)>(depthY2+height of polysilicon layer 14 of gate wiring G)/(minimum width ofelement isolation insulating film STI2)

A thickness Tm2 of the mask layer 26 in the peripheral circuit region islarger than a thickness Tm1 of the mask layer 26 in the memory cellregion.

A thickness Ts2 of the WSi film 25 in the peripheral circuit regionequals a thickness Ts1 of the WSi film 25 in the memory cell region.

A thickness Tg2 of the gate wiring G (polysilicon layers 14 and 24) inthe peripheral circuit region is smaller than a thickness Tg1 of thegate wiring (floating gate electrode FG, ONO insulating film 21, andcontrol gate electrode CG) in the memory cell region. A thickness Tg4 ofthe gate wiring (polysilicon layer 24) on the first portion STI2-A ofthe element isolation insulating film STI2 in the peripheral circuitregion is smaller than a thickness Tg3 of the gate wiring (control gateelectrode CG) on the first portion STI1-A of the element isolationinsulating film STI1 in the memory cell region.

FIGS. 3 to 11C are sectional views showing steps in manufacturing thesemiconductor memory device having the memory cell region and peripheralcircuit region according to the first embodiment of the presentinvention. FIGS. 9A, 9B, and 9C and FIGS. 11A, 11B, and 11C show detailsof the manufacturing process, including sectional views (FIGS. 9B and11B) of the peripheral circuit region shown in FIGS. 9A and 11A takenalong a vertical direction and sectional views (FIGS. 9C and 11C) of thememory cell region shown in FIGS. 9A and 11A taken along a verticaldirection. The method of manufacturing the semiconductor memory deviceaccording to the first embodiment will be described below.

First, as shown in FIG. 3, the tunnel insulating film 12 (e.g., SiO₂film) is formed on the semiconductor substrate 11 in the memory cellregion. After that, the gate insulating film (e.g., SiO₂ film) 13 isformed on the semiconductor substrate 11 in the peripheral circuitregion. The gate insulating film 13 is preferably formed thicker thanthe tunnel insulating film 12. Either of the gate insulating film 13 andtunnel insulating film 12 can be formed first. The first polysiliconlayer 14 serving as a gate wiring material is deposited. An SiN film 15serving as a chemical mechanical polish (CMP) stopper material in STIgap filling is deposited on the first polysilicon layer 14. A trench 16of the element isolation insulating film STI1 is formed in the memorycell region by reactive ion etching (RIE). A trench 17 of the elementisolation insulating film STI2 is formed in the peripheral circuitregion by RIE. The trench 17 in the peripheral circuit region is formeddeeper than the trench 16 in the memory cell region. An oxide film 18 isburied in the trenches 16 and 17. The oxide film 18 is planarized byCMP. As a result, the element isolation insulating films STI1 and STI2are formed in the memory cell region and peripheral circuit region,respectively.

As shown in FIG. 4, the element isolation insulating films STI1 and STI2are removed to a predetermined depth by wet etching by using the SiNfilm 15 as a mask. Then, the SiN film 15 is removed by hot phosphoricacid. The element isolation insulating films STI1 and STI2 may then befurther removed to a predetermined depth by wet etching. As a result,the upper surfaces of the element isolation insulating films STI1 andSTI2 become flush with, e.g., the upper surface of the first polysiliconlayer 14.

As shown in FIG. 5, a resist 19 is applied to the upper surfaces of thefirst polysilicon layer 14 and element isolation insulating films STI1and STI2 and patterned to open the memory cell region. After that, theelement isolation insulating film STI1 in the memory cell region isremoved to a predetermined depth by dry etching. Consequently, the uppersurface of the element isolation insulating film STI1 becomes lower thanthe upper surface of the first polysilicon layer 14 so that a trench 20is formed. The upper surface of the element isolation insulating filmSTI1 is preferably lower than about ½ the thickness of the firstpolysilicon layer 14 and equal to or higher than the upper surface ofthe tunnel insulating film 12.

As shown in FIG. 6, the ONO insulating film 21 is deposited on the firstpolysilicon layer 14 and element isolation insulating films STI1 andSTI2. The second polysilicon layer 22 is deposited on the ONO insulatingfilm 21. The ONO insulating film 21 is formed from an SiO₂ film/SiNfilm/SiO₂ film.

As shown in FIG. 7, a resist 23 is applied to the upper surface of thesecond polysilicon layer 22 and patterned to open the peripheral circuitregion. The second polysilicon layer 22 and ONO insulating film 21 areetched by using the patterned resist 23. With this process, the firstpolysilicon layer 14 and element isolation insulating film STI2 in theperipheral circuit region are exposed. Then, the resist 23 is removed.

As shown in FIG. 8, the third polysilicon layer 24, WSi film 25, andmask layer 26 are deposited sequentially. The WSi film 25 need notalways use W as a refractory metal. For example, Co or Ti may be used.As the mask layer 26, e.g., an SiO₂ film or SiN film is used.

As shown in FIGS. 9A to 9C, a resist 27 is applied to the upper surfaceof the mask layer 26 and processed into the gate wiring pattern. Themask layer 26, WSi film 25, third polysilicon layer 24, and secondpolysilicon layer 22 in the peripheral circuit region and memory cellregion are etched by using the patterned resist 27. Then, etching isperformed under a condition to decrease the selectivity of polysiliconto the oxide film and increase the selectivity to SiN. In the peripheralcircuit region, the first polysilicon layer 14 and element isolationinsulating film STI1 are etched so that the gate wirings are processed(FIG. 9B). In the memory cell region, etching is stopped on the uppersurface of the SiN film of the ONO insulating film 21 (FIG. 9C). Then,the resist 27 is removed.

As shown in FIGS. 10A to 10C, a resist 28 is applied to the uppersurface of the mask layer 26 and patterned to cover the peripheralcircuit region. The SiN film and SiO₂ film of the ONO insulating film 21and the first polysilicon layer 14 in the memory cell region are etchedby dry etching. This dry etching is done under a condition to lower themask layer 26 to a predetermined height. With this process, the uppersurface of the mask layer 26 in the memory cell region becomes flushwith that in the peripheral circuit region. Then, the resist 28 isremoved.

Next, as shown in FIGS. 1 and 2A to 2D, ion implantation is executed toform diffusion layers necessary for forming a transistor. Then, thespacer 29 is formed on the side surface of the gate wiring. Heavilydoped diffusion layers are formed. Next, the barrier layer 30 isdeposited. The gate wiring is buried by the insulating film 31. Theinsulating film 31 is planarized by CMP. Subsequently, the insulatingfilm 32 is formed on the insulating film 31 and barrier layer 30 andplanarized. The contacts C1 and C2 extending through the insulating film32, barrier layer 30, and mask layer 26 are formed. After a normalinterconnection layer/passivation formation process is executed, thenonvolatile memory manufacturing process is ended.

According to the first embodiment, the thickness Tm2 of the mask layer26 in the peripheral circuit region is larger than the thickness Tm1 ofthe mask layer 26 in the memory cell region. In addition, the thicknessTg2 of the gate wiring G (polysilicon layers 14 and 24) in theperipheral circuit region is smaller than the thickness Tg1 of the gatewiring (floating gate electrode FG, ONO insulating film 21, and controlgate electrode CG) in the memory cell region. Hence, even when theelement isolation insulating films STI1 and STI2 in the memory cellregion and peripheral circuit region have the different heights X1 andX2 (X1<X2), the height h1 from the upper surface of the semiconductorsubstrate 11 to the upper surface of the mask layer 26 in the memorycell region can equal the height h2 from the upper surface of thesemiconductor substrate 11 to the upper surface of the mask layer 26 inthe peripheral circuit region. For this reason, any erosion (dishing)for the barrier layer 30 in the peripheral circuit region can beprevented in CMP planarization of the buried insulating film 31 of thegate wiring.

The element isolation insulating film STI2 in the peripheral circuitregion has the large depth Y2 and large height X2. With this structure,the distance between the gate wiring and the bottom surface of theelement isolation insulating film STI2 in the peripheral circuit regioncan be increased while avoiding any gap filling failure of the elementisolation insulating film STI2 so that the element breakdown voltage canbe increased. Furthermore, since the element isolation insulating filmSTI2 can be made narrow, the chip size can further be reduced.

The upper surfaces of the second portions STI1-B and STI2-B of theelement isolation insulating films except under the gate wirings in thememory cell region and peripheral circuit region are lowered to theupper surface of the semiconductor substrate 11. With this structure,any etching residue can be prevented from being generated on the sidesof the element isolation insulating films STI1 and STI2 in the gateprocess. Hence, any short circuit between the gate wirings can beprevented.

Second Embodiment

In the first embodiment, the height h1 in the memory cell region is madeequal to the height h2 in the peripheral circuit region by adjusting thedifference (Tg1>Tg2) between the thicknesses Tg1 and Tg2 of the gatewirings by the thicknesses Tm1 and Tm2 (Tm1<Tm2) of the mask layers 26.In the second embodiment, a height h1 in the memory cell region is madeequal to a height h2 in the peripheral circuit region by makingthicknesses Tg1 and Tg2 of gate wirings equal to each other (Tg1=Tg2).

FIG. 12 is a sectional view showing a semiconductor memory device havinga memory cell region and peripheral circuit region according to thesecond embodiment of the present invention. The semiconductor memorydevice according to the second embodiment will be described below. Adescription of the same structure as in the first embodiment will beomitted.

As shown in FIG. 12, the second embodiment is different from the firstembodiment in that the height h1 from the upper surface of asemiconductor substrate 11 to the upper surface of a mask layer 26 inthe memory cell region is made equal to the height h2 from the uppersurface of the semiconductor substrate 11 to the upper surface of themask layer 26 in the peripheral circuit region by making thickness Tg1of a gate wiring (floating gate electrode FG, ONO insulating film 21,and control gate electrode CG) in the memory cell region equal to thethickness Tg2 of a gate wiring G (polysilicon layers 14, 41, and 24) inthe peripheral circuit region.

For this reason, a thickness Tm2 of the mask layer 26 in the peripheralcircuit region equals a thickness Tm1 of the mask layer 26 in the memorycell region. In addition, a thickness Ts2 of a WSi film 25 in theperipheral circuit region equals a thickness Ts1 of the WSi film 25 inthe memory cell region.

The gate wiring G in the peripheral circuit region includes the threepolysilicon layers 14, 41, and 24. The two polysilicon layers 41 and 24extend onto a first portion STI2-A of an element isolation insulatingfilm STI2. A thickness Tg4 of the gate wiring (polysilicon layers 41 and24) on the element isolation insulating film STI2 in the peripheralcircuit region is smaller than a thickness Tg3 of the gate wiring(control gate electrode CG) on an element isolation insulating film STI1in the memory cell region.

FIGS. 13 to 17 are sectional views showing steps in manufacturing thesemiconductor memory device having the memory cell region and peripheralcircuit region according to the second embodiment of the presentinvention. FIGS. 15A, 15B, and 15C and FIGS. 16A, 16B, and 16C showdetails of the manufacturing process, including sectional views (FIGS.15B and 16B) of the peripheral circuit region shown in FIGS. 15A and 16Ataken along a vertical direction and sectional views (FIGS. 15C and 16C)of the memory cell region shown in FIGS. 15A and 16A taken along avertical direction. The method of manufacturing the semiconductor memorydevice according to the second embodiment will be described below.

First, the processes shown in FIGS. 3 to 7 of the above-described firstembodiment are done. A second polysilicon layer 22 and ONO insulatingfilm 21 in the peripheral circuit region are removed so that the firstpolysilicon layer 14 and element isolation insulating film STI2 in theperipheral circuit region are exposed.

As shown in FIG. 13, the third polysilicon layer 41 is deposited. Aresist 42 is applied to the upper surface of the third polysilicon layer41 and patterned to open the memory cell region. The third polysiliconlayer 41 is etched and left only in the peripheral circuit region byusing the patterned resist 42. Then, the resist 24 is removed.

In depositing the third polysilicon layer 41, a native oxide film (notshown) is formed on the polysilicon layer 22 in the memory cell region.The native oxide film is used as a stopper in etching the thirdpolysilicon layer 41.

In the process shown in FIG. 13, the upper surface of the thirdpolysilicon layer 41 is preferably flush with the upper surface of thesecond polysilicon layer 22. For this purpose, the third polysiliconlayer 41 is deposited to the same thickness as that of the secondpolysilicon layer 22. When the second and third polysilicon layers 22and 41 are deposited to different thicknesses, a process of making theupper surfaces of the second and third polysilicon layers 22 and 41equal may be added.

As shown in FIG. 14, the fourth polysilicon layer 24, WSi film 25, andmask layer 26 are deposited sequentially on the second and thirdpolysilicon layers 22 and 41. The WSi film 25 need not always use W as arefractory metal. For example, Co or Ti may be used. As the mask layer26, e.g., an SiO₂ film or SiN film is used.

As shown in FIGS. 15A to 15C, a resist 27 is applied to the uppersurface of the mask layer 26 and processed into the gate wiring pattern.The mask layer 26, WSi film 25, fourth polysilicon layer 24, thirdpolysilicon layer 41, and first polysilicon layer 14 in the peripheralcircuit region are etched by using the patterned resist 27. With thisprocess, the gate wiring in the peripheral circuit region is processed.Then, the resist 27 is removed.

As shown in FIGS. 16A to 16C, a resist 28 is applied to the uppersurface of the mask layer 26 and processed into the gate wiring pattern.The mask layer 26, WSi film 25, fourth polysilicon layer 24, and secondpolysilicon layer 22 in the memory cell region are etched by using thepatterned resist 28. With this process, the gate wiring in the memorycell region is processed.

As shown in FIG. 17, the resist 28 is removed. In this way, the gatewirings can be formed while making the height of the mask layer 26 inthe memory cell region equal to that in the peripheral circuit region.

Next, as shown in FIG. 12, ion implantation is executed to formdiffusion layers necessary for forming a transistor. Then, a spacer 29is formed on the side surface of the gate wiring. Heavily dopeddiffusion layers are formed. Next, a barrier layer 30 is deposited. Thegate wiring is buried by an insulating film 31. The insulating film 31is planarized by CMP. Subsequently, an insulating film 32 is formed onthe insulating film 31 and barrier layer 30 and planarized. Contacts C1and C2 extending through the insulating film 32, barrier layer 30, andmask layer 26 are formed. After a normal interconnectionlayer/passivation formation process is executed, the nonvolatile memorymanufacturing process is ended.

According to the second embodiment, the same effect as in the firstembodiment can be obtained. Additionally, in the second embodiment,since the thicknesses Tm1 and Tm2 of the mask layers 26 in the memorycell region and peripheral circuit region are equal, the contacts C1 andC2 can more easily be formed than in the first embodiment.

The present invention is not limited to the above-described embodiments,and various changes and modifications can be made in practicing it. Forexample, the element isolation insulating films STI1 and STI2 need notalways be self-aligned to the gate wirings and can be formedindependently of the gate wirings. The embodiments of the presentinvention need not always be applied when the gate wirings in the memorycell region and peripheral circuit region have a level difference andcan also be applied even when the gate wirings have a level differencebetween various regions (e.g., between the memory cell regions, betweenthe peripheral circuit regions, between the memory cell region and alogic circuit region, or between the peripheral circuit region and alogic circuit region).

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details and representative embodiments shownand described herein. Accordingly, various modifications may be madewithout departing from the spirit or scope of the general inventiveconcept as defined by the appended claims and their equivalents.

1. A semiconductor memory device comprising: a semiconductor substratewhich has a first region and a second region; a first element isolationinsulating film which is formed in the semiconductor substrate in thefirst region, includes a first upper surface higher than an uppersurface of the semiconductor substrate and a first bottom surface lowerthan the upper surface of the semiconductor substrate, and has a firstheight from the upper surface of the semiconductor substrate to thefirst upper surface; a second element isolation insulating film which isformed in the semiconductor substrate in the second region, includes asecond upper surface higher than the upper surface of the semiconductorsubstrate and a second bottom surface lower than the upper surface ofthe semiconductor substrate, and has a second height from the uppersurface of the semiconductor substrate to the second upper surface, thesecond height being larger than the first height; a first gateinsulating film which is formed on the semiconductor substrate in thefirst region; a first gate wiring which is formed on the first gateinsulating film; a first mask layer which is formed on the first gatewiring; a second gate insulating film which is formed on thesemiconductor substrate in the second region; a second gate wiring whichis formed on the second gate insulating film; and a second mask layerwhich is formed on the second gate wiring, wherein a height from theupper surface of the semiconductor substrate to an upper surface of thefirst mask layer equals a height from the upper surface of thesemiconductor substrate to an upper surface of the second mask layer. 2.The device according to claim 1, wherein the first element isolationinsulating film has a first depth from the upper surface of thesemiconductor substrate to the first bottom surface, the second elementisolation insulating film has a second depth from the upper surface ofthe semiconductor substrate to the second bottom surface, and the seconddepth is larger than the first depth.
 3. The device according to claim2, wherein the first depth is larger than the first height, and thesecond depth is larger than the second height.
 4. The device accordingto claim 1, wherein a thickness of the second mask layer is larger thana thickness of the first mask layer.
 5. The device according to claim 1,wherein a thickness of the second mask layer equals a thickness of thefirst mask layer.
 6. The device according to claim 1, which furthercomprises: a first silicide layer which is provided between the firstgate wiring and the first mask layer and has a first thickness; and asecond silicide layer which is provided between the second gate wiringand the second mask layer and has a second thickness equal to the firstthickness, and in which a thickness of the first gate wiring is largerthan a thickness of the second gate wiring.
 7. The device according toclaim 1, which further comprises: a first silicide layer which isprovided between the first gate wiring and the first mask layer and hasa first thickness; and a second silicide layer which is provided betweenthe second gate wiring and the second mask layer and has a secondthickness equal to the first thickness, and in which a thickness of thefirst gate wiring equals a thickness of the second gate wiring.
 8. Thedevice according to claim 1, wherein the first element isolationinsulating film has a first portion including the first upper surfaceand the first bottom surface, and a second portion including a thirdupper surface flush with the upper surface of the semiconductorsubstrate and a third bottom surface flush with the first bottomsurface, the second element isolation insulating film has a thirdportion including the second upper surface and the second bottomsurface, and a fourth portion including a fourth upper surface flushwith the upper surface of the semiconductor substrate and a fourthbottom surface flush with the second bottom surface, the first portionis located below the first gate wiring, and the second portion islocated except below the first gate wiring, and the third portion islocated below the second gate wiring, and the fourth portion is locatedexcept below the second gate wiring.
 9. The device according to claim 1,which further comprises: a first diffusion layer which is formed in thesemiconductor substrate in the first region; and a second diffusionlayer which is formed in the semiconductor substrate in the secondregion, and in which the first depth has a level lower than a bottomsurface of the first diffusion layer, and the second depth has a levellower than a bottom surface of the second diffusion layer.
 10. Thedevice according to claim 1, further comprising: a first contact whichis arranged above the first element isolation insulating film andconnected to the first gate wiring, and a second contact which isarranged above the second element isolation insulating film andconnected to the second gate wiring.
 11. The device according to claim1, wherein a thickness of the first gate wiring is smaller than athickness of the second gate wiring.
 12. The device according to claim1, wherein the first region is a memory cell region, and the secondregion is a peripheral circuit region, and the first gate wiring has afloating gate electrode provided on the first gate insulating film, acontrol gate electrode provided above the floating gate electrode, andan insulating film provided between the floating gate electrode and thecontrol gate electrode.
 13. A semiconductor memory device manufacturingmethod comprising: in a semiconductor substrate having a first regionand a second region, forming a first gate insulating film on thesemiconductor substrate in the first region and forming a second gateinsulating film on the semiconductor substrate in the second region;forming a first gate wiring material on the first gate insulating filmand the second gate insulating film; forming a first element isolationinsulating film by partially removing the first gate wiring material,the first gate insulating film, and the semiconductor substrate andforming a second element isolation insulating film by partially removingthe first gate wiring material, the second gate insulating film, and thesemiconductor substrate; making a first height from an upper surface ofthe semiconductor substrate to an upper surface of the first elementisolation insulating film smaller than a second height from the uppersurface of the semiconductor substrate to an upper surface of the secondelement isolation insulating film by removing an upper portion of thefirst element isolation insulating film; forming a second gate wiringmaterial, third gate wiring material, and first mask layer sequentiallyin the first region and forming a fourth gate wiring material and asecond mask layer sequentially in the second region; and removing anupper portion of the first mask layer to make a height from the uppersurface of the semiconductor substrate to an upper surface of the firstmask layer equal to a height from the upper surface of the semiconductorsubstrate to an upper surface of the second mask layer.
 14. The methodaccording to claim 13, wherein a second depth from the upper surface ofthe semiconductor substrate to a bottom surface of the second elementisolation insulating film is larger than a first depth from the uppersurface of the semiconductor substrate to a bottom surface of the firstelement isolation insulating film.
 15. The method according to claim 13,wherein in processing the first gate wiring material, the second gatewiring material, and the third gate wiring material in the first region,the upper portion of the first mask layer is removed.
 16. The methodaccording to claim 13, further comprising forming a first contact abovethe first element isolation insulating film and forming a second contactabove the second element isolation insulating film.
 17. The methodaccording to claim 13, wherein the first region is a memory cell region,and the second region is a peripheral circuit region, and in the memorycell region, the first gate wiring material functions as a floating gateelectrode, the second gate wiring material and the third gate wiringmaterial function as a control gate electrode, and an insulating film isprovided between the floating gate electrode and the control gateelectrode.
 18. A semiconductor memory device manufacturing methodcomprising: in a semiconductor substrate having a first region and asecond region, forming a first gate insulating film on the semiconductorsubstrate in the first region and forming a second gate insulating filmon the semiconductor substrate in the second region; forming a firstgate wiring material on the first gate insulating film and the secondgate insulating film; forming a first element isolation insulating filmby partially removing the first gate wiring material, the first gateinsulating film, and the semiconductor substrate and forming a secondelement isolation insulating film by partially removing the first gatewiring material, the second gate insulating film, and the semiconductorsubstrate; making a first height from an upper surface of thesemiconductor substrate to an upper surface of the first elementisolation insulating film smaller than a second height from the uppersurface of the semiconductor substrate to an upper surface of the secondelement isolation insulating film by removing an upper portion of thefirst element isolation insulating film; forming a second gate wiringmaterial in the first region, forming a third gate wiring material inthe second region, and making upper surfaces of the second gate wiringmaterial and the third gate wiring material flush with each other; andforming a first mask layer on the second gate wiring material andforming a second mask layer on the third gate wiring material.
 19. Themethod according to claim 18, wherein a thickness of the second masklayer equals a thickness of the first mask layer.
 20. The methodaccording to claim 18, wherein the first region is a memory cell region,and the second region is a peripheral circuit region, and in the memorycell region, the first gate wiring material functions as a floating gateelectrode, the second gate wiring material functions as a control gateelectrode, and an insulating film is provided between the floating gateelectrode and the control gate electrode.